Test MP+PPO746

PPC MP+PPO746
"Fre LwSyncdWW Rfe DpDatadW PosWR PosRW PosWR DpCtrldW PosWR"
Cycle=Rfe DpDatadW PosWR PosRW PosWR DpCtrldW PosWR Fre LwSyncdWW
Relax=
Safe=Rfe Fre PosWR PosRW LwSyncdWW DpDatadW DpCtrldW
Prefetch=1:x=T
Com=Rf Fr
Orig=Fre LwSyncdWW Rfe DpDatadW PosWR PosRW PosWR DpCtrldW PosWR
{
0:r2=x; 0:r4=y;
1:r2=y; 1:r4=z; 1:r9=x;
}
 P0           | P1            ;
 li r1,2      | lwz r1,0(r2)  ;
 stw r1,0(r2) | xor r3,r1,r1  ;
 lwsync       | addi r3,r3,1  ;
 li r3,1      | stw r3,0(r4)  ;
 stw r3,0(r4) | lwz r5,0(r4)  ;
              | li r6,2       ;
              | stw r6,0(r4)  ;
              | lwz r7,0(r4)  ;
              | cmpw r7,r7    ;
              | beq  LC00     ;
              | LC00:         ;
              | li r8,1       ;
              | stw r8,0(r9)  ;
              | lwz r10,0(r9) ;
exists
(x=2 /\ z=2 /\ 1:r1=1 /\ 1:r10=1)