Test MP+PPO716

PPC MP+PPO716
"Fre LwSyncdWW Rfe PosRR DpAddrdR DpDatadW PosWR DpCtrldW PosWR"
Cycle=Rfe PosRR DpAddrdR DpDatadW PosWR DpCtrldW PosWR Fre LwSyncdWW
Relax=
Safe=Rfe Fre PosWR PosRR LwSyncdWW DpAddrdR DpDatadW DpCtrldW
Prefetch=1:x=T
Com=Rf Fr
Orig=Fre LwSyncdWW Rfe PosRR DpAddrdR DpDatadW PosWR DpCtrldW PosWR
{
0:r2=x; 0:r4=y;
1:r2=y; 1:r6=z; 1:r8=a; 1:r11=x;
}
 P0           | P1             ;
 li r1,2      | lwz r1,0(r2)   ;
 stw r1,0(r2) | lwz r3,0(r2)   ;
 lwsync       | xor r4,r3,r3   ;
 li r3,1      | lwzx r5,r4,r6  ;
 stw r3,0(r4) | xor r7,r5,r5   ;
              | addi r7,r7,1   ;
              | stw r7,0(r8)   ;
              | lwz r9,0(r8)   ;
              | cmpw r9,r9     ;
              | beq  LC00      ;
              | LC00:          ;
              | li r10,1       ;
              | stw r10,0(r11) ;
              | lwz r12,0(r11) ;
exists
(x=2 /\ 1:r1=1 /\ 1:r12=1)