Test MP+PPO626

PPC MP+PPO626
"Fre LwSyncdWW Rfe DpDatadW PosWR DpDatadW PosWR DpDatadW PosWR"
Cycle=Rfe DpDatadW PosWR DpDatadW PosWR DpDatadW PosWR Fre LwSyncdWW
Relax=
Safe=Rfe Fre PosWR LwSyncdWW DpDatadW
Prefetch=1:x=T
Com=Rf Fr
Orig=Fre LwSyncdWW Rfe DpDatadW PosWR DpDatadW PosWR DpDatadW PosWR
{
0:r2=x; 0:r4=y;
1:r2=y; 1:r4=z; 1:r7=a; 1:r10=x;
}
 P0           | P1             ;
 li r1,2      | lwz r1,0(r2)   ;
 stw r1,0(r2) | xor r3,r1,r1   ;
 lwsync       | addi r3,r3,1   ;
 li r3,1      | stw r3,0(r4)   ;
 stw r3,0(r4) | lwz r5,0(r4)   ;
              | xor r6,r5,r5   ;
              | addi r6,r6,1   ;
              | stw r6,0(r7)   ;
              | lwz r8,0(r7)   ;
              | xor r9,r8,r8   ;
              | addi r9,r9,1   ;
              | stw r9,0(r10)  ;
              | lwz r11,0(r10) ;
exists
(x=2 /\ 1:r1=1 /\ 1:r11=1)