Test MP+PPO596

PPC MP+PPO596
"Fre LwSyncdWW Rfe PosRR DpDatadW PosWR DpAddrdR DpDatadW PosWR"
Cycle=Rfe PosRR DpDatadW PosWR DpAddrdR DpDatadW PosWR Fre LwSyncdWW
Relax=
Safe=Rfe Fre PosWR PosRR LwSyncdWW DpAddrdR DpDatadW
Prefetch=1:x=T
Com=Rf Fr
Orig=Fre LwSyncdWW Rfe PosRR DpDatadW PosWR DpAddrdR DpDatadW PosWR
{
0:r2=x; 0:r4=y;
1:r2=y; 1:r5=z; 1:r9=a; 1:r11=x;
}
 P0           | P1             ;
 li r1,2      | lwz r1,0(r2)   ;
 stw r1,0(r2) | lwz r3,0(r2)   ;
 lwsync       | xor r4,r3,r3   ;
 li r3,1      | addi r4,r4,1   ;
 stw r3,0(r4) | stw r4,0(r5)   ;
              | lwz r6,0(r5)   ;
              | xor r7,r6,r6   ;
              | lwzx r8,r7,r9  ;
              | xor r10,r8,r8  ;
              | addi r10,r10,1 ;
              | stw r10,0(r11) ;
              | lwz r12,0(r11) ;
exists
(x=2 /\ 1:r1=1 /\ 1:r12=1)