Test MP+PPO432

PPC MP+PPO432
"Fre LwSyncdWW Rfe PosRR DpAddrdW PosWR DpAddrdR PosRR DpCtrlIsyncdR"
Cycle=Rfe PosRR DpAddrdW PosWR DpAddrdR PosRR DpCtrlIsyncdR Fre LwSyncdWW
Relax=
Safe=Rfe Fre PosWR PosRR LwSyncdWW DpAddrdW DpAddrdR DpCtrlIsyncdR
Prefetch=1:x=T
Com=Rf Fr
Orig=Fre LwSyncdWW Rfe PosRR DpAddrdW PosWR DpAddrdR PosRR DpCtrlIsyncdR
{
0:r2=x; 0:r4=y;
1:r2=y; 1:r6=z; 1:r10=a; 1:r13=x;
}
 P0           | P1             ;
 li r1,1      | lwz r1,0(r2)   ;
 stw r1,0(r2) | lwz r3,0(r2)   ;
 lwsync       | xor r4,r3,r3   ;
 li r3,1      | li r5,1        ;
 stw r3,0(r4) | stwx r5,r4,r6  ;
              | lwz r7,0(r6)   ;
              | xor r8,r7,r7   ;
              | lwzx r9,r8,r10 ;
              | lwz r11,0(r10) ;
              | cmpw r11,r11   ;
              | beq  LC00      ;
              | LC00:          ;
              | isync          ;
              | lwz r12,0(r13) ;
exists
(1:r1=1 /\ 1:r12=0)