Test MP+PPO388

PPC MP+PPO388
"Fre LwSyncdWW Rfe DpCtrldW PosWR DpDatadW PosWW PosWR DpCtrlIsyncdR"
Cycle=Rfe DpCtrldW PosWR DpDatadW PosWW PosWR DpCtrlIsyncdR Fre LwSyncdWW
Relax=
Safe=Rfe Fre PosWW PosWR LwSyncdWW DpDatadW DpCtrldW DpCtrlIsyncdR
Prefetch=1:x=T
Com=Rf Fr
Orig=Fre LwSyncdWW Rfe DpCtrldW PosWR DpDatadW PosWW PosWR DpCtrlIsyncdR
{
0:r2=x; 0:r4=y;
1:r2=y; 1:r4=z; 1:r7=a; 1:r11=x;
}
 P0           | P1             ;
 li r1,1      | lwz r1,0(r2)   ;
 stw r1,0(r2) | cmpw r1,r1     ;
 lwsync       | beq  LC00      ;
 li r3,1      | LC00:          ;
 stw r3,0(r4) | li r3,1        ;
              | stw r3,0(r4)   ;
              | lwz r5,0(r4)   ;
              | xor r6,r5,r5   ;
              | addi r6,r6,1   ;
              | stw r6,0(r7)   ;
              | li r8,2        ;
              | stw r8,0(r7)   ;
              | lwz r9,0(r7)   ;
              | cmpw r9,r9     ;
              | beq  LC01      ;
              | LC01:          ;
              | isync          ;
              | lwz r10,0(r11) ;
exists
(a=2 /\ 1:r1=1 /\ 1:r10=0)