Test MP+PPO340

PPC MP+PPO340
"Fre LwSyncdWW Rfe DpAddrdW PosWR PosRR DpDatadW PosWR DpCtrlIsyncdR"
Cycle=Rfe DpAddrdW PosWR PosRR DpDatadW PosWR DpCtrlIsyncdR Fre LwSyncdWW
Relax=
Safe=Rfe Fre PosWR PosRR LwSyncdWW DpAddrdW DpDatadW DpCtrlIsyncdR
Prefetch=1:x=T
Com=Rf Fr
Orig=Fre LwSyncdWW Rfe DpAddrdW PosWR PosRR DpDatadW PosWR DpCtrlIsyncdR
{
0:r2=x; 0:r4=y;
1:r2=y; 1:r5=z; 1:r9=a; 1:r12=x;
}
 P0           | P1             ;
 li r1,1      | lwz r1,0(r2)   ;
 stw r1,0(r2) | xor r3,r1,r1   ;
 lwsync       | li r4,1        ;
 li r3,1      | stwx r4,r3,r5  ;
 stw r3,0(r4) | lwz r6,0(r5)   ;
              | lwz r7,0(r5)   ;
              | xor r8,r7,r7   ;
              | addi r8,r8,1   ;
              | stw r8,0(r9)   ;
              | lwz r10,0(r9)  ;
              | cmpw r10,r10   ;
              | beq  LC00      ;
              | LC00:          ;
              | isync          ;
              | lwz r11,0(r12) ;
exists
(1:r1=1 /\ 1:r11=0)