Test MP+PPO282

PPC MP+PPO282
"Fre LwSyncdWW Rfe DpAddrdR PosRW PosWR PosRR DpAddrdR DpCtrlIsyncdR"
Cycle=Rfe DpAddrdR PosRW PosWR PosRR DpAddrdR DpCtrlIsyncdR Fre LwSyncdWW
Relax=
Safe=Rfe Fre PosWR PosRW PosRR LwSyncdWW DpAddrdR DpCtrlIsyncdR
Prefetch=1:x=T
Com=Rf Fr
Orig=Fre LwSyncdWW Rfe DpAddrdR PosRW PosWR PosRR DpAddrdR DpCtrlIsyncdR
{
0:r2=x; 0:r4=y;
1:r2=y; 1:r5=z; 1:r11=a; 1:r13=x;
}
 P0           | P1              ;
 li r1,1      | lwz r1,0(r2)    ;
 stw r1,0(r2) | xor r3,r1,r1    ;
 lwsync       | lwzx r4,r3,r5   ;
 li r3,1      | li r6,1         ;
 stw r3,0(r4) | stw r6,0(r5)    ;
              | lwz r7,0(r5)    ;
              | lwz r8,0(r5)    ;
              | xor r9,r8,r8    ;
              | lwzx r10,r9,r11 ;
              | cmpw r10,r10    ;
              | beq  LC00       ;
              | LC00:           ;
              | isync           ;
              | lwz r12,0(r13)  ;
exists
(1:r1=1 /\ 1:r12=0)