Test MP+PPO264

PPC MP+PPO264
"Fre LwSyncdWW Rfe DpDatadW PosWR DpAddrdR PosRR DpAddrdR DpCtrlIsyncdR"
Cycle=Rfe DpDatadW PosWR DpAddrdR PosRR DpAddrdR DpCtrlIsyncdR Fre LwSyncdWW
Relax=
Safe=Rfe Fre PosWR PosRR LwSyncdWW DpAddrdR DpDatadW DpCtrlIsyncdR
Prefetch=1:x=T
Com=Rf Fr
Orig=Fre LwSyncdWW Rfe DpDatadW PosWR DpAddrdR PosRR DpAddrdR DpCtrlIsyncdR
{
0:r2=x; 0:r4=y;
1:r2=y; 1:r4=z; 1:r8=a; 1:r12=b; 1:r14=x;
}
 P0           | P1               ;
 li r1,1      | lwz r1,0(r2)     ;
 stw r1,0(r2) | xor r3,r1,r1     ;
 lwsync       | addi r3,r3,1     ;
 li r3,1      | stw r3,0(r4)     ;
 stw r3,0(r4) | lwz r5,0(r4)     ;
              | xor r6,r5,r5     ;
              | lwzx r7,r6,r8    ;
              | lwz r9,0(r8)     ;
              | xor r10,r9,r9    ;
              | lwzx r11,r10,r12 ;
              | cmpw r11,r11     ;
              | beq  LC00        ;
              | LC00:            ;
              | isync            ;
              | lwz r13,0(r14)   ;
exists
(1:r1=1 /\ 1:r13=0)