Test MP+PPO240

PPC MP+PPO240
"Fre LwSyncdWW Rfe PosRW PosWR DpCtrldW PosWR DpAddrdR DpCtrlIsyncdR"
Cycle=Rfe PosRW PosWR DpCtrldW PosWR DpAddrdR DpCtrlIsyncdR Fre LwSyncdWW
Relax=
Safe=Rfe Fre PosWR PosRW LwSyncdWW DpAddrdR DpCtrldW DpCtrlIsyncdR
Prefetch=1:x=T
Com=Rf Fr
Orig=Fre LwSyncdWW Rfe PosRW PosWR DpCtrldW PosWR DpAddrdR DpCtrlIsyncdR
{
0:r2=x; 0:r4=y;
1:r2=y; 1:r6=z; 1:r10=a; 1:r12=x;
}
 P0           | P1             ;
 li r1,1      | lwz r1,0(r2)   ;
 stw r1,0(r2) | li r3,2        ;
 lwsync       | stw r3,0(r2)   ;
 li r3,1      | lwz r4,0(r2)   ;
 stw r3,0(r4) | cmpw r4,r4     ;
              | beq  LC00      ;
              | LC00:          ;
              | li r5,1        ;
              | stw r5,0(r6)   ;
              | lwz r7,0(r6)   ;
              | xor r8,r7,r7   ;
              | lwzx r9,r8,r10 ;
              | cmpw r9,r9     ;
              | beq  LC01      ;
              | LC01:          ;
              | isync          ;
              | lwz r11,0(r12) ;
exists
(y=2 /\ 1:r1=1 /\ 1:r11=0)