Test MP+PPO128

PPC MP+PPO128
"Fre LwSyncdWW Rfe DpAddrdR PosRR DpAddrdR PosRW PosWR DpAddrdR"
Cycle=Rfe DpAddrdR PosRR DpAddrdR PosRW PosWR DpAddrdR Fre LwSyncdWW
Relax=
Safe=Rfe Fre PosWR PosRW PosRR LwSyncdWW DpAddrdR
Prefetch=1:x=T
Com=Rf Fr
Orig=Fre LwSyncdWW Rfe DpAddrdR PosRR DpAddrdR PosRW PosWR DpAddrdR
{
0:r2=x; 0:r4=y;
1:r2=y; 1:r5=z; 1:r9=a; 1:r14=x;
}
 P0           | P1               ;
 li r1,1      | lwz r1,0(r2)     ;
 stw r1,0(r2) | xor r3,r1,r1     ;
 lwsync       | lwzx r4,r3,r5    ;
 li r3,1      | lwz r6,0(r5)     ;
 stw r3,0(r4) | xor r7,r6,r6     ;
              | lwzx r8,r7,r9    ;
              | li r10,1         ;
              | stw r10,0(r9)    ;
              | lwz r11,0(r9)    ;
              | xor r12,r11,r11  ;
              | lwzx r13,r12,r14 ;
exists
(1:r1=1 /\ 1:r13=0)