Test MP+PPO104

PPC MP+PPO104
"Fre LwSyncdWW Rfe DpDatadW PosWR DpDatadW PosWW PosWR DpAddrdR"
Cycle=Rfe DpDatadW PosWR DpDatadW PosWW PosWR DpAddrdR Fre LwSyncdWW
Relax=
Safe=Rfe Fre PosWW PosWR LwSyncdWW DpAddrdR DpDatadW
Prefetch=1:x=T
Com=Rf Fr
Orig=Fre LwSyncdWW Rfe DpDatadW PosWR DpDatadW PosWW PosWR DpAddrdR
{
0:r2=x; 0:r4=y;
1:r2=y; 1:r4=z; 1:r7=a; 1:r12=x;
}
 P0           | P1               ;
 li r1,1      | lwz r1,0(r2)     ;
 stw r1,0(r2) | xor r3,r1,r1     ;
 lwsync       | addi r3,r3,1     ;
 li r3,1      | stw r3,0(r4)     ;
 stw r3,0(r4) | lwz r5,0(r4)     ;
              | xor r6,r5,r5     ;
              | addi r6,r6,1     ;
              | stw r6,0(r7)     ;
              | li r8,2          ;
              | stw r8,0(r7)     ;
              | lwz r9,0(r7)     ;
              | xor r10,r9,r9    ;
              | lwzx r11,r10,r12 ;
exists
(a=2 /\ 1:r1=1 /\ 1:r11=0)