Test MP+PPO014

PPC MP+PPO014
"Fre LwSyncdWW Rfe PosRR DpDatadW PosWR DpAddrdW PosWR DpAddrdR"
Cycle=Rfe PosRR DpDatadW PosWR DpAddrdW PosWR DpAddrdR Fre LwSyncdWW
Relax=
Safe=Rfe Fre PosWR PosRR LwSyncdWW DpAddrdW DpAddrdR DpDatadW
Prefetch=1:x=T
Com=Rf Fr
Orig=Fre LwSyncdWW Rfe PosRR DpDatadW PosWR DpAddrdW PosWR DpAddrdR
{
0:r2=x; 0:r4=y;
1:r2=y; 1:r5=z; 1:r9=a; 1:r13=x;
}
 P0           | P1               ;
 li r1,1      | lwz r1,0(r2)     ;
 stw r1,0(r2) | lwz r3,0(r2)     ;
 lwsync       | xor r4,r3,r3     ;
 li r3,1      | addi r4,r4,1     ;
 stw r3,0(r4) | stw r4,0(r5)     ;
              | lwz r6,0(r5)     ;
              | xor r7,r6,r6     ;
              | li r8,1          ;
              | stwx r8,r7,r9    ;
              | lwz r10,0(r9)    ;
              | xor r11,r10,r10  ;
              | lwzx r12,r11,r13 ;
exists
(1:r1=1 /\ 1:r12=0)