Test 2+2W0001

PPC 2+2W0001
"LwSyncdWW Wse PodWR DpAddrdR DpAddrdW Wse"
Cycle=Wse PodWR DpAddrdR DpAddrdW Wse LwSyncdWW
Relax=[Wse,LwSyncdWW,Wse]
Safe=PodWR DpAddrdW DpAddrdR
Prefetch=0:x=F,0:y=W,1:y=F,1:x=W
Com=Ws Ws
Orig=LwSyncdWW Wse PodWR DpAddrdR DpAddrdW Wse
{
0:r2=x; 0:r4=y;
1:r2=y; 1:r4=z; 1:r7=a; 1:r10=x;
}
 P0           | P1             ;
 li r1,2      | li r1,2        ;
 stw r1,0(r2) | stw r1,0(r2)   ;
 lwsync       | lwz r3,0(r4)   ;
 li r3,1      | xor r5,r3,r3   ;
 stw r3,0(r4) | lwzx r6,r5,r7  ;
              | xor r8,r6,r6   ;
              | li r9,1        ;
              | stwx r9,r8,r10 ;
exists
(x=2 /\ y=2)