Test Z6.2+dmb+dsb+dsb.st

ARM Z6.2+dmb+dsb+dsb.st
"DMBdWW Rfe DSBdRW Rfe DSB.STdRW Wse"
Cycle=Rfe DSBdRW Rfe DSB.STdRW Wse DMBdWW
Prefetch=0:x=F,0:y=W,1:y=F,1:z=W,2:z=F,2:x=W
Com=Rf Rf Ws
Orig=DMBdWW Rfe DSBdRW Rfe DSB.STdRW Wse
{
%x0=x; %y0=y;
%y1=y; %z1=z;
%z2=z; %x2=x;
}
 P0           | P1           | P2           ;
 MOV R0,#2    | LDR R0,[%y1] | LDR R0,[%z2] ;
 STR R0,[%x0] | DSB          | DSB ST       ;
 DMB          | MOV R1,#1    | MOV R1,#1    ;
 MOV R1,#1    | STR R1,[%z1] | STR R1,[%x2] ;
 STR R1,[%y0] |              |              ;
Observed
    1:R0=1; 2:R0=1; x=2;