Test WRC+dsb+dsb.st

ARM WRC+dsb+dsb.st
"Rfe DSBdRW Rfe DSB.STdRR Fre"
Cycle=Rfe DSBdRW Rfe DSB.STdRR Fre
Prefetch=0:x=T,1:x=F,1:y=W,2:y=F,2:x=T
Com=Rf Rf Fr
Orig=Rfe DSBdRW Rfe DSB.STdRR Fre
{
%x0=x;
%x1=x; %y1=y;
%y2=y; %x2=x;
}
 P0           | P1           | P2           ;
 MOV R0,#1    | LDR R0,[%x1] | LDR R0,[%y2] ;
 STR R0,[%x0] | DSB          | DSB ST       ;
              | MOV R1,#1    | LDR R1,[%x2] ;
              | STR R1,[%y1] |              ;
Observed
    1:R0=1; 2:R0=1; 2:R1=0;