Test R0022

ARM R0022
"DMBdWW Wse PosWR DpCtrldW PosWR Fre"
Cycle=Fre DMBdWW Wse PosWR DpCtrldW PosWR
Relax=[Fre,DMBdWW,Wse]
Safe=PosWR DpCtrldW
Prefetch=0:x=F,0:y=W,1:y=F,1:x=T
Com=Ws Fr
Orig=DMBdWW Wse PosWR DpCtrldW PosWR Fre
{
%x0=x; %y0=y;
%y1=y; %x1=x;
}
 P0           | P1           ;
 MOV R0,#2    | MOV R0,#2    ;
 STR R0,[%x0] | STR R0,[%y1] ;
 DMB          | LDR R1,[%y1] ;
 MOV R1,#1    | CMP R1,R1    ;
 STR R1,[%y0] | BNE LC00     ;
              | LC00:        ;
              | MOV R2,#1    ;
              | STR R2,[%x1] ;
              | LDR R3,[%x1] ;
Observed
    1:R3=2; x=2; y=2;