Test MP0161

ARM MP0161
"DMBdWW Rfe DpAddrdR DpDatadW PodWR Fre"
Cycle=Rfe DpAddrdR DpDatadW PodWR Fre DMBdWW
Relax=[Fre,DMBdWW,Rfe]
Safe=PodWR DpAddrdR DpDatadW
Prefetch=0:x=F,0:y=W,1:y=F,1:x=T
Com=Rf Fr
Orig=DMBdWW Rfe DpAddrdR DpDatadW PodWR Fre
{
%x0=x; %y0=y;
%y1=y; %z1=z; %a1=a; %x1=x;
}
 P0           | P1              ;
 MOV R0,#1    | LDR R0,[%y1]    ;
 STR R0,[%x0] | EOR R1,R0,R0    ;
 DMB          | LDR R2,[R1,%z1] ;
 MOV R1,#1    | EOR R3,R2,R2    ;
 STR R1,[%y0] | ADD R3,R3,#1    ;
              | STR R3,[%a1]    ;
              | LDR R4,[%x1]    ;
Observed
    1:R0=1; 1:R4=0;