Test MP+dmb+dmb.st

ARM MP+dmb+dmb.st
"DMBdWW Rfe DMB.STdRR Fre"
Cycle=Rfe DMB.STdRR Fre DMBdWW
Prefetch=0:x=F,0:y=W,1:y=F,1:x=T
Com=Rf Fr
Orig=DMBdWW Rfe DMB.STdRR Fre
{
%x0=x; %y0=y;
%y1=y; %x1=x;
}
 P0           | P1           ;
 MOV R0,#1    | LDR R0,[%y1] ;
 STR R0,[%x0] | DMB ST       ;
 DMB          | LDR R1,[%x1] ;
 MOV R1,#1    |              ;
 STR R1,[%y0] |              ;
Observed
    1:R0=1; 1:R1=0;