Test MP+PPO842

ARM MP+PPO842
"Fre DMBdWW Rfe DpAddrdR PosRW PosWR DpAddrdR PosRR"
Cycle=Rfe DpAddrdR PosRW PosWR DpAddrdR PosRR Fre DMBdWW
Relax=
Safe=Rfe Fre PosWR PosRW PosRR DMBdWW DpAddrdR
Prefetch=1:x=T
Orig=Fre DMBdWW Rfe DpAddrdR PosRW PosWR DpAddrdR PosRR
{
%x0=x; %y0=y;
%y1=y; %z1=z; %x1=x;
}
 P0            | P1               ;
 MOV R0, #1    | LDR R0, [%y1]    ;
 STR R0, [%x0] | EOR R1,R0,R0     ;
 DMB           | LDR R2, [R1,%z1] ;
 MOV R1, #1    | MOV R3, #1       ;
 STR R1, [%y0] | STR R3, [%z1]    ;
               | LDR R4, [%z1]    ;
               | EOR R5,R4,R4     ;
               | LDR R6, [R5,%x1] ;
               | LDR R7, [%x1]    ;
Observed
    1:R0=1; 1:R7=0;