Test MP+PPO835

ARM MP+PPO835
"Fre DMBdWW Rfe DpAddrdR DpDatadW PosWW PosWR DpAddrdR PosRR"
Cycle=Rfe DpAddrdR DpDatadW PosWW PosWR DpAddrdR PosRR Fre DMBdWW
Relax=
Safe=Rfe Fre PosWW PosWR PosRR DMBdWW DpAddrdR DpDatadW
Prefetch=1:x=T
Orig=Fre DMBdWW Rfe DpAddrdR DpDatadW PosWW PosWR DpAddrdR PosRR
{
%x0=x; %y0=y;
%y1=y; %z1=z; %a1=a; %x1=x;
}
 P0            | P1               ;
 MOV R0, #1    | LDR R0, [%y1]    ;
 STR R0, [%x0] | EOR R1,R0,R0     ;
 DMB           | LDR R2, [R1,%z1] ;
 MOV R1, #1    | EOR R3,R2,R2     ;
 STR R1, [%y0] | ADD R3, R3, #1   ;
               | STR R3, [%a1]    ;
               | MOV R4, #2       ;
               | STR R4, [%a1]    ;
               | LDR R5, [%a1]    ;
               | EOR R6,R5,R5     ;
               | LDR R7, [R6,%x1] ;
               | LDR R8, [%x1]    ;
Observed
    1:R0=1; 1:R8=0; a=2;