Test MP+PPO826

ARM MP+PPO826
"Fre DMBdWW Rfe DpDatadW PosWR DpCtrldW PosWR DpAddrdR PosRR"
Cycle=Rfe DpDatadW PosWR DpCtrldW PosWR DpAddrdR PosRR Fre DMBdWW
Relax=
Safe=Rfe Fre PosWR PosRR DMBdWW DpAddrdR DpDatadW DpCtrldW
Prefetch=1:x=T
Orig=Fre DMBdWW Rfe DpDatadW PosWR DpCtrldW PosWR DpAddrdR PosRR
{
%x0=x; %y0=y;
%y1=y; %z1=z; %a1=a; %x1=x;
}
 P0            | P1               ;
 MOV R0, #1    | LDR R0, [%y1]    ;
 STR R0, [%x0] | EOR R1,R0,R0     ;
 DMB           | ADD R1, R1, #1   ;
 MOV R1, #1    | STR R1, [%z1]    ;
 STR R1, [%y0] | LDR R2, [%z1]    ;
               | CMP R2, R2       ;
               | BNE LC00         ;
               | LC00:            ;
               | MOV R3, #1       ;
               | STR R3, [%a1]    ;
               | LDR R4, [%a1]    ;
               | EOR R5,R4,R4     ;
               | LDR R6, [R5,%x1] ;
               | LDR R7, [%x1]    ;
Observed
    1:R0=1; 1:R7=0;