Test MP+PPO203

ARM MP+PPO203
"Fre DMBdWW Rfe DpAddrdR DpCtrldW PosWW PosWR PosRR DpAddrdR"
Cycle=Rfe DpAddrdR DpCtrldW PosWW PosWR PosRR DpAddrdR Fre DMBdWW
Relax=
Safe=Rfe Fre PosWW PosWR PosRR DMBdWW DpAddrdR DpCtrldW
Prefetch=1:x=T
Orig=Fre DMBdWW Rfe DpAddrdR DpCtrldW PosWW PosWR PosRR DpAddrdR
{
%x0=x; %y0=y;
%y1=y; %z1=z; %a1=a; %x1=x;
}
 P0            | P1               ;
 MOV R0, #1    | LDR R0, [%y1]    ;
 STR R0, [%x0] | EOR R1,R0,R0     ;
 DMB           | LDR R2, [R1,%z1] ;
 MOV R1, #1    | CMP R2, R2       ;
 STR R1, [%y0] | BNE LC00         ;
               | LC00:            ;
               | MOV R3, #1       ;
               | STR R3, [%a1]    ;
               | MOV R4, #2       ;
               | STR R4, [%a1]    ;
               | LDR R5, [%a1]    ;
               | LDR R6, [%a1]    ;
               | EOR R7,R6,R6     ;
               | LDR R8, [R7,%x1] ;
Observed
    1:R0=1; 1:R8=0; a=2;