Test MP+PPO127

ARM MP+PPO127
"Fre DMBdWW Rfe PosRR DpAddrdR PosRW PosWR DpAddrdR"
Cycle=Rfe PosRR DpAddrdR PosRW PosWR DpAddrdR Fre DMBdWW
Relax=
Safe=Rfe Fre PosWR PosRW PosRR DMBdWW DpAddrdR
Prefetch=1:x=T
Orig=Fre DMBdWW Rfe PosRR DpAddrdR PosRW PosWR DpAddrdR
{
%x0=x; %y0=y;
%y1=y; %z1=z; %x1=x;
}
 P0            | P1               ;
 MOV R0, #1    | LDR R0, [%y1]    ;
 STR R0, [%x0] | LDR R1, [%y1]    ;
 DMB           | EOR R2,R1,R1     ;
 MOV R1, #1    | LDR R3, [R2,%z1] ;
 STR R1, [%y0] | MOV R4, #1       ;
               | STR R4, [%z1]    ;
               | LDR R5, [%z1]    ;
               | EOR R6,R5,R5     ;
               | LDR R7, [R6,%x1] ;
Observed
    1:R0=1; 1:R7=0;