Test S+dmb+pos-fri-rfi-pos-addr-data

Executions for behaviour: "1:R0=1 ; 1:R1=0 ; 1:R3=2 ; 1:R4=2 ; x=1 ; y=2"

Executions for behaviour: "1:R0=0 ; 1:R1=1 ; 1:R3=2 ; 1:R4=2 ; x=2 ; y=2"

Executions for behaviour: "1:R0=1 ; 1:R1=1 ; 1:R3=2 ; 1:R4=2 ; x=2 ; y=2"

ARM S+dmb+pos-fri-rfi-pos-addr-data
"DMBdWW Rfe PosRR Fri Rfi PosRR DpAddrdR DpDatadW Wse"
Cycle=Rfi PosRR DpAddrdR DpDatadW Wse DMBdWW Rfe PosRR Fri
Prefetch=0:x=F,0:y=W,1:y=F,1:x=W
Com=Rf Ws
Orig=DMBdWW Rfe PosRR Fri Rfi PosRR DpAddrdR DpDatadW Wse
{
%x0=x; %y0=y;
%y1=y; %z1=z; %x1=x;
}
 P0           | P1              ;
 MOV R0,#2    | LDR R0,[%y1]    ;
 STR R0,[%x0] | LDR R1,[%y1]    ;
 DMB          | MOV R2,#2       ;
 MOV R1,#1    | STR R2,[%y1]    ;
 STR R1,[%y0] | LDR R3,[%y1]    ;
              | LDR R4,[%y1]    ;
              | EOR R5,R4,R4    ;
              | LDR R6,[R5,%z1] ;
              | EOR R7,R6,R6    ;
              | ADD R7,R7,#1    ;
              | STR R7,[%x1]    ;
Observed
    1:R0=1; 1:R1=0; 1:R3=2; 1:R4=2; x=1; y=2;
and 1:R0=0; 1:R1=1; 1:R3=2; 1:R4=2; x=2; y=2;
and 1:R0=1; 1:R1=1; 1:R3=2; 1:R4=2; x=2; y=2;