Test LB+data+RDWI+addr+WW

Executions for behaviour: "0:R0=1 ; 1:R0=1 ; 1:R2=2 ; x=2"

ARM LB+data+RDWI+addr+WW
"PodWW Rfe DpDatadW Rfe Fri Rfi DpAddrdW"
Prefetch=
Com=Rf Rf
Orig=PodWW Rfe DpDatadW Rfe Fri Rfi DpAddrdW
{
%z0=z; %x0=x;
%x1=x; %y1=y; %z1=z;
}
 P0           | P1              ;
 LDR R0,[%z0] | LDR R0,[%x1]    ;
 EOR R1,R0,R0 | MOV R1,#2       ;
 ADD R1,R1,#1 | STR R1,[%x1]    ;
 STR R1,[%x0] | LDR R2,[%x1]    ;
              | EOR R3,R2,R2    ;
              | MOV R4,#1       ;
              | STR R4,[R3,%y1] ;
              | MOV R5,#1       ;
              | STR R5,[%z1]    ;
Observed
    0:R0=1; 1:R0=1; 1:R2=2; x=2;