Test LB+PPO0116

Executions for behaviour: "0:R0=1 ; 1:R0=1 ; x=2"

ARM LB+PPO0116
"PodWW Rfe DpDatadW Rfe PosRR PosRW PosWR DpAddrdW"
Cycle=Rfe PosRR PosRW PosWR DpAddrdW PodWW Rfe DpDatadW
Relax=
Safe=Rfe PosWR PosRW PosRR Pod*W DpAddrdW DpDatadW
Prefetch=
Com=Rf Rf
Orig=PodWW Rfe DpDatadW Rfe PosRR PosRW PosWR DpAddrdW
{
%z0=z; %x0=x;
%x1=x; %y1=y; %z1=z;
}
 P0           | P1              ;
 LDR R0,[%z0] | LDR R0,[%x1]    ;
 EOR R1,R0,R0 | LDR R1,[%x1]    ;
 ADD R1,R1,#1 | MOV R2,#2       ;
 STR R1,[%x0] | STR R2,[%x1]    ;
              | LDR R3,[%x1]    ;
              | EOR R4,R3,R3    ;
              | MOV R5,#1       ;
              | STR R5,[R4,%y1] ;
              | MOV R6,#1       ;
              | STR R6,[%z1]    ;
Observed
    0:R0=1; 1:R0=1; x=2;