Model vs. ARM

• Contents

This note gives a complete comparison of our model with ARM hardware. As illustrated by the numerous tests of the table “Forbidden by model and observed”, ARM hardware contradicts our model. Refer to this companion page for an analysis.

We first provide a selection of some behaviours from the complete “Forbidden by model and observed” table. This selection first presents the test CoRR1, which is the archetype of the read-after-read hazard anomaly. We also show the more sophisticated CO-RSDWI, which includes CoRR1 as a sub-test. One may notice that our runs of these two tests demontrate observation of the read-after-read hazard anomaly on all tested machines.

The test MP+dmb+fri-rfi-ctrlisb, observed on Qualcomm APQ8060 only, is claimed by ARM designers to be legal. Although the very test MP+dmb+fri-rfi-ctrlisb is not observed on the more modern APQ8064, we have observed similar behaviours on this system. Some examples of those are LB+data+fri-rfi-ctrl, LB+data+data-wsi-rfi-ctrl, S+dmb+fri-rfi-ctrl. We logically think that those similar behaviours should also be considered legal.

Other tests are examples of invalid behaviours that are observed much less often and only on (quite ancient) quad-core systems Tegra3 and Exynos4412. We think those should not be considered legal — See the companion document for details on those “bizarre” tests. We here present two such behaviours: a coherence anomaly MOREDETOUR0052, and a violation of the MP+dmb+ctrlisb idiom included in the more complex MP+dmb+pos-ctrlisb+BIS.

• Comparing Model and ARM hardware
  • Forbidden by model and observed
  • Allowed by model and unobserved
• Specific behaviours
  • Tegra2
  • APQ8060
  • A5X
  • A6X
  • Exynos5250
  • Denver32
  • Tegra3
  • Exynos4412
  • Exynos5410
  • APQ8064
  • BCM2836
  • PI3B
  • Cortex-A72
• New this round

This document was translated from L^AT_EX by H^EV^EA.