Executions for behaviour:
"0:R0=1 ; 0:R1=2 ; 1:R0=1 ; 2:R0=1 ; ok=1 ; x=2"
ARM Z6.2+rfiar-datarna+addr+data
"RfiAR DpDatadWRNa Rfe DpAddrdW Rfe DpDatadW WseNaA"
Cycle=RfiAR DpDatadWRNa Rfe DpAddrdW Rfe DpDatadW WseNaA
Prefetch=0:x=F,0:y=W,1:y=F,1:z=W,2:z=F,2:x=W
Com=Rf Rf Ws
Orig=RfiAR DpDatadWRNa Rfe DpAddrdW Rfe DpDatadW WseNaA
{ ok=1;
%x0=x; %y0=y; %ok0=ok;
%y1=y; %z1=z;
%z2=z; %x2=x;
}
P0 | P1 | P2 ;
MOV %T3,#2 | LDR R0,[%y1] | LDR R0,[%z2] ;
LDREX R0,[%x0] | EOR R1,R0,R0 | EOR R1,R0,R0 ;
STREX %T2,%T3,[%x0] | MOV R2,#1 | ADD R1,R1,#1 ;
CMP %T2,#0 | STR R2,[R1,%z1] | STR R1,[%x2] ;
BNE Fail0 | | ;
LDREX R1,[%x0] | | ;
EOR R2,R1,R1 | | ;
ADD R2,R2,#1 | | ;
STR R2,[%y0] | | ;
B Exit0 | | ;
Fail0: | | ;
MOV R3,#0 | | ;
STR R3,[%ok0] | | ;
Exit0: | | ;
Observed
0:R0=1; 0:R1=2; 1:R0=1; 2:R0=1; ok=1; x=2;