Test WWC+poana+addrra+A

Executions for behaviour: "0:R0=0 ; 1:R0=2 ; 2:R0=1 ; 2:R2=0 ; ok=0 ; x=2"

Executions for behaviour: "0:R0=1 ; 1:R0=2 ; 2:R0=1 ; 2:R2=0 ; ok=1 ; x=2"

ARM WWC+poana+addrra+A
"RfeAA PodRWANa RfeNaR DpAddrdWRA WseAA"
Cycle=RfeNaR DpAddrdWRA WseAA RfeAA PodRWANa
Prefetch=1:x=F,1:y=W,2:y=F,2:x=W
Com=Rf Rf Ws
Orig=RfeAA PodRWANa RfeNaR DpAddrdWRA WseAA
{ ok=1;
%x0=x; %ok0=ok;
%x1=x; %y1=y; %ok1=ok;
%y2=y; %x2=x; %ok2=ok;
}
 P0                  | P1                 | P2                  ;
 MOV %T3,#2          | LDREX R0,[%x1]     | LDREX R0,[%y2]      ;
 LDREX R0,[%x0]      | STREX %T2,R0,[%x1] | EOR R1,R0,R0        ;
 STREX %T2,%T3,[%x0] | CMP %T2,#0         | ADD %T1,R1,%x2      ;
 CMP %T2,#0          | BNE Fail1          | MOV %T3,#1          ;
 BNE Fail0           | MOV R1,#1          | LDREX R2,[%T1]      ;
 B Exit0             | STR R1,[%y1]       | STREX %T2,%T3,[%T1] ;
 Fail0:              | B Exit1            | CMP %T2,#0          ;
 MOV R1,#0           | Fail1:             | BNE Fail2           ;
 STR R1,[%ok0]       | MOV R2,#0          | B Exit2             ;
 Exit0:              | STR R2,[%ok1]      | Fail2:              ;
                     | Exit1:             | MOV R3,#0           ;
                     |                    | STR R3,[%ok2]       ;
                     |                    | Exit2:              ;
Observed
    0:R0=0; 1:R0=2; 2:R0=1; 2:R2=0; ok=0; x=2;
and 0:R0=1; 1:R0=2; 2:R0=1; 2:R2=0; ok=1; x=2;