Test WWC+addrra+dmb+A

Executions for behaviour: "0:R0=1 ; 1:R0=2 ; 1:R2=0 ; 2:R0=1 ; ok=1 ; x=2 ; y=1"

ARM WWC+addrra+dmb+A
"RfeAR DpAddrdWRA RfeANa DMBdRW WseNaA"
Cycle=RfeANa DMBdRW WseNaA RfeAR DpAddrdWRA
Prefetch=1:x=F,1:y=W,2:y=F,2:x=W
Com=Rf Rf Ws
Orig=RfeAR DpAddrdWRA RfeANa DMBdRW WseNaA
{ ok=1;
%x0=x; %ok0=ok;
%x1=x; %y1=y; %ok1=ok;
%y2=y; %x2=x;
}
 P0                  | P1                  | P2           ;
 MOV %T3,#2          | LDREX R0,[%x1]      | LDR R0,[%y2] ;
 LDREX R0,[%x0]      | EOR R1,R0,R0        | DMB          ;
 STREX %T2,%T3,[%x0] | ADD %T1,R1,%y1      | MOV R1,#1    ;
 CMP %T2,#0          | MOV %T3,#1          | STR R1,[%x2] ;
 BNE Fail0           | LDREX R2,[%T1]      |              ;
 B Exit0             | STREX %T2,%T3,[%T1] |              ;
 Fail0:              | CMP %T2,#0          |              ;
 MOV R1,#0           | BNE Fail1           |              ;
 STR R1,[%ok0]       | B Exit1             |              ;
 Exit0:              | Fail1:              |              ;
                     | MOV R3,#0           |              ;
                     | STR R3,[%ok1]       |              ;
                     | Exit1:              |              ;
Observed
    0:R0=1; 1:R0=2; 1:R2=0; 2:R0=1; ok=1; x=2; y=1;