Test WWC+addrana+addrnaa

Executions for behaviour: "1:R0=2 ; 2:R0=1 ; 2:R2=0 ; ok=0 ; x=2"

Executions for behaviour: "1:R0=2 ; 2:R0=1 ; 2:R2=0 ; ok=1 ; x=2"

ARM WWC+addrana+addrnaa
"RfeNaA DpAddrdWANa Rfe DpAddrdWNaA WseANa"
Cycle=Rfe DpAddrdWNaA WseANa RfeNaA DpAddrdWANa
Prefetch=1:x=F,1:y=W,2:y=F,2:x=W
Com=Rf Rf Ws
Orig=RfeNaA DpAddrdWANa Rfe DpAddrdWNaA WseANa
{ ok=1;
%x0=x;
%x1=x; %y1=y; %ok1=ok;
%y2=y; %x2=x; %ok2=ok;
}
 P0           | P1                 | P2                  ;
 MOV R0,#2    | LDREX R0,[%x1]     | LDR R0,[%y2]        ;
 STR R0,[%x0] | STREX %T2,R0,[%x1] | EOR R1,R0,R0        ;
              | CMP %T2,#0         | ADD %T1,R1,%x2      ;
              | BNE Fail1          | MOV %T3,#1          ;
              | EOR R1,R0,R0       | LDREX R2,[%T1]      ;
              | MOV R2,#1          | STREX %T2,%T3,[%T1] ;
              | STR R2,[R1,%y1]    | CMP %T2,#0          ;
              | B Exit1            | BNE Fail2           ;
              | Fail1:             | B Exit2             ;
              | MOV R3,#0          | Fail2:              ;
              | STR R3,[%ok1]      | MOV R3,#0           ;
              | Exit1:             | STR R3,[%ok2]       ;
              |                    | Exit2:              ;
Observed
    1:R0=2; 2:R0=1; 2:R2=0; ok=0; x=2;
and 1:R0=2; 2:R0=1; 2:R2=0; ok=1; x=2;