Test WRW+2W+poana+poaa

Executions for behaviour: "1:R0=1 ; 2:R0=1 ; 2:R1=2 ; ok=1 ; x=1 ; y=2"

Executions for behaviour: "1:R0=1 ; 2:R0=1 ; 2:R1=0 ; ok=1 ; x=2 ; y=2"

Executions for behaviour: "1:R0=2 ; 2:R0=1 ; 2:R1=0 ; ok=1 ; x=2 ; y=2"

ARM WRW+2W+poana+poaa
"RfeNaA PodRWANa WseNaA PodWWAA WseANa"
Cycle=RfeNaA PodRWANa WseNaA PodWWAA WseANa
Prefetch=1:x=F,1:y=W,2:y=F,2:x=W
Com=Rf Ws Ws
Orig=RfeNaA PodRWANa WseNaA PodWWAA WseANa
{ ok=1;
%x0=x;
%x1=x; %y1=y; %ok1=ok;
%y2=y; %x2=x; %ok2=ok;
}
 P0           | P1                 | P2                  ;
 MOV R0,#2    | LDREX R0,[%x1]     | MOV %T3,#2          ;
 STR R0,[%x0] | STREX %T2,R0,[%x1] | LDREX R0,[%y2]      ;
              | CMP %T2,#0         | STREX %T2,%T3,[%y2] ;
              | BNE Fail1          | CMP %T2,#0          ;
              | MOV R1,#1          | BNE Fail2           ;
              | STR R1,[%y1]       | MOV %T3,#1          ;
              | B Exit1            | LDREX R1,[%x2]      ;
              | Fail1:             | STREX %T2,%T3,[%x2] ;
              | MOV R2,#0          | CMP %T2,#0          ;
              | STR R2,[%ok1]      | BNE Fail2           ;
              | Exit1:             | B Exit2             ;
              |                    | Fail2:              ;
              |                    | MOV R2,#0           ;
              |                    | STR R2,[%ok2]       ;
              |                    | Exit2:              ;
Observed
    1:R0=1; 2:R0=1; 2:R1=2; ok=1; x=1; y=2;
and 1:R0=1; 2:R0=1; 2:R1=0; ok=1; x=2; y=2;
and 1:R0=2; 2:R0=1; 2:R1=0; ok=1; x=2; y=2;