Test WRR+2W+addrrr+dmbnaa+A

Executions for behaviour: "0:R0=0 ; 1:R0=2 ; 1:R2=0 ; 2:R1=0 ; ok=0 ; x=2"

Executions for behaviour: "0:R0=1 ; 1:R0=2 ; 1:R2=0 ; 2:R1=0 ; ok=1 ; x=2"

ARM WRR+2W+addrrr+dmbnaa+A
"RfeAR DpAddrdRRR FreRNa DMBdWWNaA WseAA"
Cycle=RfeAR DpAddrdRRR FreRNa DMBdWWNaA WseAA
Prefetch=1:x=F,1:y=T,2:y=F,2:x=W
Com=Rf Fr Ws
Orig=RfeAR DpAddrdRRR FreRNa DMBdWWNaA WseAA
{ ok=1;
%x0=x; %ok0=ok;
%x1=x; %y1=y;
%y2=y; %x2=x; %ok2=ok;
}
 P0                  | P1             | P2                  ;
 MOV %T3,#2          | LDREX R0,[%x1] | MOV R0,#1           ;
 LDREX R0,[%x0]      | EOR R1,R0,R0   | STR R0,[%y2]        ;
 STREX %T2,%T3,[%x0] | ADD %T1,R1,%y1 | DMB                 ;
 CMP %T2,#0          | LDREX R2,[%T1] | MOV %T3,#1          ;
 BNE Fail0           |                | LDREX R1,[%x2]      ;
 B Exit0             |                | STREX %T2,%T3,[%x2] ;
 Fail0:              |                | CMP %T2,#0          ;
 MOV R1,#0           |                | BNE Fail2           ;
 STR R1,[%ok0]       |                | B Exit2             ;
 Exit0:              |                | Fail2:              ;
                     |                | MOV R2,#0           ;
                     |                | STR R2,[%ok2]       ;
                     |                | Exit2:              ;
Observed
    0:R0=0; 1:R0=2; 1:R2=0; 2:R1=0; ok=0; x=2;
and 0:R0=1; 1:R0=2; 1:R2=0; 2:R1=0; ok=1; x=2;