Test WRR+2W+addrnaa+poana

Executions for behaviour: "1:R0=1 ; 1:R2=0 ; 2:R0=0 ; ok=0 ; x=1 ; y=1"

Executions for behaviour: "1:R0=1 ; 1:R2=0 ; 2:R0=0 ; ok=1 ; x=1 ; y=1"

Executions for behaviour: "1:R0=1 ; 1:R2=0 ; 2:R0=0 ; ok=0 ; x=2 ; y=1"

Executions for behaviour: "1:R0=1 ; 1:R2=0 ; 2:R0=0 ; ok=1 ; x=2 ; y=1"

ARM WRR+2W+addrnaa+poana
"Rfe DpAddrdRNaA FreAA PodWWANa Wse"
Cycle=Rfe DpAddrdRNaA FreAA PodWWANa Wse
Prefetch=1:x=F,1:y=T,2:y=F,2:x=W
Com=Rf Fr Ws
Orig=Rfe DpAddrdRNaA FreAA PodWWANa Wse
{ ok=1;
%x0=x;
%x1=x; %y1=y; %ok1=ok;
%y2=y; %x2=x; %ok2=ok;
}
 P0           | P1                 | P2                  ;
 MOV R0,#2    | LDR R0,[%x1]       | MOV %T3,#1          ;
 STR R0,[%x0] | EOR R1,R0,R0       | LDREX R0,[%y2]      ;
              | ADD %T1,R1,%y1     | STREX %T2,%T3,[%y2] ;
              | LDREX R2,[%T1]     | CMP %T2,#0          ;
              | STREX %T2,R2,[%T1] | BNE Fail2           ;
              | CMP %T2,#0         | MOV R1,#1           ;
              | BNE Fail1          | STR R1,[%x2]        ;
              | B Exit1            | B Exit2             ;
              | Fail1:             | Fail2:              ;
              | MOV R3,#0          | MOV R2,#0           ;
              | STR R3,[%ok1]      | STR R2,[%ok2]       ;
              | Exit1:             | Exit2:              ;
Observed
    1:R0=1; 1:R2=0; 2:R0=0; ok=0; x=1; y=1;
and 1:R0=1; 1:R2=0; 2:R0=0; ok=1; x=1; y=1;
and 1:R0=1; 1:R2=0; 2:R0=0; ok=0; x=2; y=1;
and 1:R0=1; 1:R2=0; 2:R0=0; ok=1; x=2; y=1;