Test WRC+poana+ctrlisbra

Executions for behaviour: "1:R0=1 ; 2:R0=1 ; 2:R1=0 ; ok=0 ; x=1"

Executions for behaviour: "1:R0=1 ; 2:R0=1 ; 2:R1=0 ; ok=1 ; x=1"

ARM WRC+poana+ctrlisbra
"RfeNaA PodRWANa RfeNaR DpCtrlIsbdRRA FreANa"
Cycle=RfeNaA PodRWANa RfeNaR DpCtrlIsbdRRA FreANa
Prefetch=1:x=F,1:y=W,2:y=F,2:x=T
Com=Rf Rf Fr
Orig=RfeNaA PodRWANa RfeNaR DpCtrlIsbdRRA FreANa
{ ok=1;
%x0=x;
%x1=x; %y1=y; %ok1=ok;
%y2=y; %x2=x; %ok2=ok;
}
 P0           | P1                 | P2                 ;
 MOV R0,#1    | LDREX R0,[%x1]     | LDREX R0,[%y2]     ;
 STR R0,[%x0] | STREX %T2,R0,[%x1] | CMP R0,R0          ;
              | CMP %T2,#0         | BNE LC00           ;
              | BNE Fail1          | LC00:              ;
              | MOV R1,#1          | ISB                ;
              | STR R1,[%y1]       | LDREX R1,[%x2]     ;
              | B Exit1            | STREX %T2,R1,[%x2] ;
              | Fail1:             | CMP %T2,#0         ;
              | MOV R2,#0          | BNE Fail2          ;
              | STR R2,[%ok1]      | B Exit2            ;
              | Exit1:             | Fail2:             ;
              |                    | MOV R2,#0          ;
              |                    | STR R2,[%ok2]      ;
              |                    | Exit2:             ;
Observed
    1:R0=1; 2:R0=1; 2:R1=0; ok=0; x=1;
and 1:R0=1; 2:R0=1; 2:R1=0; ok=1; x=1;