Test WRC+ctrlisbnaas+A

Executions for behaviour: "0:R0=0 ; 1:R0=1 ; 1:R1=0 ; 2:R0=1 ; 2:R1=0 ; ok=0 ; x=1 ; y=1"

Executions for behaviour: "0:R0=0 ; 1:R0=1 ; 1:R1=0 ; 2:R0=1 ; 2:R1=0 ; ok=1 ; x=1 ; y=1"

ARM WRC+ctrlisbnaas+A
"RfeANa DpCtrlIsbdWNaA RfeANa DpCtrlIsbdRNaA FreAA"
Cycle=RfeANa DpCtrlIsbdWNaA RfeANa DpCtrlIsbdRNaA FreAA
Prefetch=1:x=F,1:y=W,2:y=F,2:x=T
Com=Rf Rf Fr
Orig=RfeANa DpCtrlIsbdWNaA RfeANa DpCtrlIsbdRNaA FreAA
{ ok=1;
%x0=x; %ok0=ok;
%x1=x; %y1=y; %ok1=ok;
%y2=y; %x2=x; %ok2=ok;
}
 P0                  | P1                  | P2                 ;
 MOV %T3,#1          | LDR R0,[%x1]        | LDR R0,[%y2]       ;
 LDREX R0,[%x0]      | CMP R0,R0           | CMP R0,R0          ;
 STREX %T2,%T3,[%x0] | BNE LC00            | BNE LC01           ;
 CMP %T2,#0          | LC00:               | LC01:              ;
 BNE Fail0           | ISB                 | ISB                ;
 B Exit0             | MOV %T3,#1          | LDREX R1,[%x2]     ;
 Fail0:              | LDREX R1,[%y1]      | STREX %T2,R1,[%x2] ;
 MOV R1,#0           | STREX %T2,%T3,[%y1] | CMP %T2,#0         ;
 STR R1,[%ok0]       | CMP %T2,#0          | BNE Fail2          ;
 Exit0:              | BNE Fail1           | B Exit2            ;
                     | B Exit1             | Fail2:             ;
                     | Fail1:              | MOV R2,#0          ;
                     | MOV R2,#0           | STR R2,[%ok2]      ;
                     | STR R2,[%ok1]       | Exit2:             ;
                     | Exit1:              |                    ;
Observed
    0:R0=0; 1:R0=1; 1:R1=0; 2:R0=1; 2:R1=0; ok=0; x=1; y=1;
and 0:R0=0; 1:R0=1; 1:R1=0; 2:R0=1; 2:R1=0; ok=1; x=1; y=1;