Test WRC+ctrlisbaa+ctrlisb

Executions for behaviour: "1:R0=1 ; 1:R1=0 ; 2:R0=1 ; 2:R1=0 ; ok=1 ; x=1 ; y=1"

ARM WRC+ctrlisbaa+ctrlisb
"RfeNaA DpCtrlIsbdWAA RfeANa DpCtrlIsbdR Fre"
Cycle=RfeNaA DpCtrlIsbdWAA RfeANa DpCtrlIsbdR Fre
Prefetch=1:x=F,1:y=W,2:y=F,2:x=T
Com=Rf Rf Fr
Orig=RfeNaA DpCtrlIsbdWAA RfeANa DpCtrlIsbdR Fre
{ ok=1;
%x0=x;
%x1=x; %y1=y; %ok1=ok;
%y2=y; %x2=x;
}
 P0           | P1                  | P2           ;
 MOV R0,#1    | LDREX R0,[%x1]      | LDR R0,[%y2] ;
 STR R0,[%x0] | STREX %T2,R0,[%x1]  | CMP R0,R0    ;
              | CMP %T2,#0          | BNE LC01     ;
              | BNE Fail1           | LC01:        ;
              | CMP R0,R0           | ISB          ;
              | BNE LC00            | LDR R1,[%x2] ;
              | LC00:               |              ;
              | ISB                 |              ;
              | MOV %T3,#1          |              ;
              | LDREX R1,[%y1]      |              ;
              | STREX %T2,%T3,[%y1] |              ;
              | CMP %T2,#0          |              ;
              | BNE Fail1           |              ;
              | B Exit1             |              ;
              | Fail1:              |              ;
              | MOV R2,#0           |              ;
              | STR R2,[%ok1]       |              ;
              | Exit1:              |              ;
Observed
    1:R0=1; 1:R1=0; 2:R0=1; 2:R1=0; ok=1; x=1; y=1;