Test WRC+ctrlana+addrra

Executions for behaviour: "1:R0=1 ; 2:R0=1 ; 2:R2=0 ; ok=0 ; x=1"

Executions for behaviour: "1:R0=1 ; 2:R0=1 ; 2:R2=0 ; ok=1 ; x=1"

ARM WRC+ctrlana+addrra
"RfeNaA DpCtrldWANa RfeNaR DpAddrdRRA FreANa"
Cycle=RfeNaA DpCtrldWANa RfeNaR DpAddrdRRA FreANa
Prefetch=1:x=F,1:y=W,2:y=F,2:x=T
Com=Rf Rf Fr
Orig=RfeNaA DpCtrldWANa RfeNaR DpAddrdRRA FreANa
{ ok=1;
%x0=x;
%x1=x; %y1=y; %ok1=ok;
%y2=y; %x2=x; %ok2=ok;
}
 P0           | P1                 | P2                 ;
 MOV R0,#1    | LDREX R0,[%x1]     | LDREX R0,[%y2]     ;
 STR R0,[%x0] | STREX %T2,R0,[%x1] | EOR R1,R0,R0       ;
              | CMP %T2,#0         | ADD %T1,R1,%x2     ;
              | BNE Fail1          | LDREX R2,[%T1]     ;
              | CMP R0,R0          | STREX %T2,R2,[%T1] ;
              | BNE LC00           | CMP %T2,#0         ;
              | LC00:              | BNE Fail2          ;
              | MOV R1,#1          | B Exit2            ;
              | STR R1,[%y1]       | Fail2:             ;
              | B Exit1            | MOV R3,#0          ;
              | Fail1:             | STR R3,[%ok2]      ;
              | MOV R2,#0          | Exit2:             ;
              | STR R2,[%ok1]      |                    ;
              | Exit1:             |                    ;
Observed
    1:R0=1; 2:R0=1; 2:R2=0; ok=0; x=1;
and 1:R0=1; 2:R0=1; 2:R2=0; ok=1; x=1;