Executions for behaviour:
"0:R0=0 ; 1:R0=1 ; 2:R0=1 ; 2:R1=0 ; ok=1 ; x=1 ; y=1"
ARM WRC+ctrl+ctrlisbaa+A
"RfeANa DpCtrldW RfeNaA DpCtrlIsbdRAA FreAA"
Cycle=RfeNaA DpCtrlIsbdRAA FreAA RfeANa DpCtrldW
Prefetch=1:x=F,1:y=W,2:y=F,2:x=T
Com=Rf Rf Fr
Orig=RfeANa DpCtrldW RfeNaA DpCtrlIsbdRAA FreAA
{ ok=1;
%x0=x; %ok0=ok;
%x1=x; %y1=y;
%y2=y; %x2=x; %ok2=ok;
}
P0 | P1 | P2 ;
MOV %T3,#1 | LDR R0,[%x1] | LDREX R0,[%y2] ;
LDREX R0,[%x0] | CMP R0,R0 | STREX %T2,R0,[%y2] ;
STREX %T2,%T3,[%x0] | BNE LC00 | CMP %T2,#0 ;
CMP %T2,#0 | LC00: | BNE Fail2 ;
BNE Fail0 | MOV R1,#1 | CMP R0,R0 ;
B Exit0 | STR R1,[%y1] | BNE LC01 ;
Fail0: | | LC01: ;
MOV R1,#0 | | ISB ;
STR R1,[%ok0] | | LDREX R1,[%x2] ;
Exit0: | | STREX %T2,R1,[%x2] ;
| | CMP %T2,#0 ;
| | BNE Fail2 ;
| | B Exit2 ;
| | Fail2: ;
| | MOV R2,#0 ;
| | STR R2,[%ok2] ;
| | Exit2: ;
Observed
0:R0=0; 1:R0=1; 2:R0=1; 2:R1=0; ok=1; x=1; y=1;