Test WRC+addraa+ctrlisbnar

Executions for behaviour: "1:R0=1 ; 1:R2=0 ; 2:R0=1 ; 2:R1=0 ; ok=1 ; x=1 ; y=1"

ARM WRC+addraa+ctrlisbnar
"RfeNaA DpAddrdWAA RfeANa DpCtrlIsbdRNaR FreRNa"
Cycle=RfeNaA DpAddrdWAA RfeANa DpCtrlIsbdRNaR FreRNa
Prefetch=1:x=F,1:y=W,2:y=F,2:x=T
Com=Rf Rf Fr
Orig=RfeNaA DpAddrdWAA RfeANa DpCtrlIsbdRNaR FreRNa
{ ok=1;
%x0=x;
%x1=x; %y1=y; %ok1=ok;
%y2=y; %x2=x;
}
 P0           | P1                  | P2             ;
 MOV R0,#1    | LDREX R0,[%x1]      | LDR R0,[%y2]   ;
 STR R0,[%x0] | STREX %T2,R0,[%x1]  | CMP R0,R0      ;
              | CMP %T2,#0          | BNE LC00       ;
              | BNE Fail1           | LC00:          ;
              | EOR R1,R0,R0        | ISB            ;
              | ADD %T1,R1,%y1      | LDREX R1,[%x2] ;
              | MOV %T3,#1          |                ;
              | LDREX R2,[%T1]      |                ;
              | STREX %T2,%T3,[%T1] |                ;
              | CMP %T2,#0          |                ;
              | BNE Fail1           |                ;
              | B Exit1             |                ;
              | Fail1:              |                ;
              | MOV R3,#0           |                ;
              | STR R3,[%ok1]       |                ;
              | Exit1:              |                ;
Observed
    1:R0=1; 1:R2=0; 2:R0=1; 2:R1=0; ok=1; x=1; y=1;