Test RWC+ctrlaa+dmbana

Executions for behaviour: "1:R0=1 ; 1:R1=0 ; 2:R0=0 ; 2:R1=0 ; ok=1 ; x=1 ; y=1"

ARM RWC+ctrlaa+dmbana
"RfeNaA DpCtrldRAA FreAA DMBdWRANa Fre"
Cycle=RfeNaA DpCtrldRAA FreAA DMBdWRANa Fre
Prefetch=1:x=F,1:y=T,2:y=F,2:x=T
Com=Rf Fr Fr
Orig=RfeNaA DpCtrldRAA FreAA DMBdWRANa Fre
{ ok=1;
%x0=x;
%x1=x; %y1=y; %ok1=ok;
%y2=y; %x2=x; %ok2=ok;
}
 P0           | P1                 | P2                  ;
 MOV R0,#1    | LDREX R0,[%x1]     | MOV %T3,#1          ;
 STR R0,[%x0] | STREX %T2,R0,[%x1] | LDREX R0,[%y2]      ;
              | CMP %T2,#0         | STREX %T2,%T3,[%y2] ;
              | BNE Fail1          | CMP %T2,#0          ;
              | CMP R0,R0          | BNE Fail2           ;
              | BNE LC00           | DMB                 ;
              | LC00:              | LDR R1,[%x2]        ;
              | LDREX R1,[%y1]     | B Exit2             ;
              | STREX %T2,R1,[%y1] | Fail2:              ;
              | CMP %T2,#0         | MOV R2,#0           ;
              | BNE Fail1          | STR R2,[%ok2]       ;
              | B Exit1            | Exit2:              ;
              | Fail1:             |                     ;
              | MOV R2,#0          |                     ;
              | STR R2,[%ok1]      |                     ;
              | Exit1:             |                     ;
Observed
    1:R0=1; 1:R1=0; 2:R0=0; 2:R1=0; ok=1; x=1; y=1;