Test RWC+addrrr+dmbnar+A

Executions for behaviour: "0:R0=0 ; 1:R0=1 ; 1:R2=0 ; 2:R1=0 ; ok=1 ; x=1"

ARM RWC+addrrr+dmbnar+A
"RfeAR DpAddrdRRR FreRNa DMBdWRNaR FreRA"
Cycle=RfeAR DpAddrdRRR FreRNa DMBdWRNaR FreRA
Prefetch=1:x=F,1:y=T,2:y=F,2:x=T
Com=Rf Fr Fr
Orig=RfeAR DpAddrdRRR FreRNa DMBdWRNaR FreRA
{ ok=1;
%x0=x; %ok0=ok;
%x1=x; %y1=y;
%y2=y; %x2=x;
}
 P0                  | P1             | P2             ;
 MOV %T3,#1          | LDREX R0,[%x1] | MOV R0,#1      ;
 LDREX R0,[%x0]      | EOR R1,R0,R0   | STR R0,[%y2]   ;
 STREX %T2,%T3,[%x0] | ADD %T1,R1,%y1 | DMB            ;
 CMP %T2,#0          | LDREX R2,[%T1] | LDREX R1,[%x2] ;
 BNE Fail0           |                |                ;
 B Exit0             |                |                ;
 Fail0:              |                |                ;
 MOV R1,#0           |                |                ;
 STR R1,[%ok0]       |                |                ;
 Exit0:              |                |                ;
Observed
    0:R0=0; 1:R0=1; 1:R2=0; 2:R1=0; ok=1; x=1;