Test R+rfiana-data+rfiana-addr

Executions for behaviour: "0:R0=0 ; 0:R1=1 ; 1:R0=0 ; 1:R1=1 ; 1:R3=0 ; ok=1 ; x=1 ; y=1"

ARM R+rfiana-data+rfiana-addr
"RfiANa DpDatadW WseNaA RfiANa DpAddrdR FreNaA"
Cycle=RfiANa DpAddrdR FreNaA RfiANa DpDatadW WseNaA
Prefetch=0:x=F,0:y=W,1:y=F,1:x=T
Com=Ws Fr
Orig=RfiANa DpDatadW WseNaA RfiANa DpAddrdR FreNaA
{ ok=1;
%x0=x; %y0=y; %ok0=ok;
%y1=y; %x1=x; %ok1=ok;
}
 P0                  | P1                  ;
 MOV %T3,#1          | MOV %T3,#2          ;
 LDREX R0,[%x0]      | LDREX R0,[%y1]      ;
 STREX %T2,%T3,[%x0] | STREX %T2,%T3,[%y1] ;
 CMP %T2,#0          | CMP %T2,#0          ;
 BNE Fail0           | BNE Fail1           ;
 LDR R1,[%x0]        | LDR R1,[%y1]        ;
 EOR R2,R1,R1        | EOR R2,R1,R1        ;
 ADD R2,R2,#1        | LDR R3,[R2,%x1]     ;
 STR R2,[%y0]        | B Exit1             ;
 B Exit0             | Fail1:              ;
 Fail0:              | MOV R4,#0           ;
 MOV R3,#0           | STR R4,[%ok1]       ;
 STR R3,[%ok0]       | Exit1:              ;
 Exit0:              |                     ;
Observed
    0:R0=0; 0:R1=1; 1:R0=0; 1:R1=1; 1:R3=0; ok=1; x=1; y=1;