Test R+poaa+dmbnar

Executions for behaviour: "0:R0=0 ; 0:R1=0 ; 1:R1=0 ; ok=1 ; x=1 ; y=2"

ARM R+poaa+dmbnar
"PodWWAA WseANa DMBdWRNaR FreRA"
Cycle=FreRA PodWWAA WseANa DMBdWRNaR
Prefetch=0:x=F,0:y=W,1:y=F,1:x=T
Com=Ws Fr
Orig=PodWWAA WseANa DMBdWRNaR FreRA
{ ok=1;
%x0=x; %y0=y; %ok0=ok;
%y1=y; %x1=x;
}
 P0                  | P1             ;
 MOV %T3,#1          | MOV R0,#2      ;
 LDREX R0,[%x0]      | STR R0,[%y1]   ;
 STREX %T2,%T3,[%x0] | DMB            ;
 CMP %T2,#0          | LDREX R1,[%x1] ;
 BNE Fail0           |                ;
 MOV %T3,#1          |                ;
 LDREX R1,[%y0]      |                ;
 STREX %T2,%T3,[%y0] |                ;
 CMP %T2,#0          |                ;
 BNE Fail0           |                ;
 B Exit0             |                ;
 Fail0:              |                ;
 MOV R2,#0           |                ;
 STR R2,[%ok0]       |                ;
 Exit0:              |                ;
Observed
    0:R0=0; 0:R1=0; 1:R1=0; ok=1; x=1; y=2;