Test MP+poana+ctrlisbaa

Executions for behaviour: "0:R0=0 ; 1:R0=1 ; 1:R1=0 ; ok=1 ; x=1 ; y=1"

ARM MP+poana+ctrlisbaa
"PodWWANa RfeNaA DpCtrlIsbdRAA FreAA"
Cycle=RfeNaA DpCtrlIsbdRAA FreAA PodWWANa
Prefetch=0:x=F,0:y=W,1:y=F,1:x=T
Com=Rf Fr
Orig=PodWWANa RfeNaA DpCtrlIsbdRAA FreAA
{ ok=1;
%x0=x; %y0=y; %ok0=ok;
%y1=y; %x1=x; %ok1=ok;
}
 P0                  | P1                 ;
 MOV %T3,#1          | LDREX R0,[%y1]     ;
 LDREX R0,[%x0]      | STREX %T2,R0,[%y1] ;
 STREX %T2,%T3,[%x0] | CMP %T2,#0         ;
 CMP %T2,#0          | BNE Fail1          ;
 BNE Fail0           | CMP R0,R0          ;
 MOV R1,#1           | BNE LC00           ;
 STR R1,[%y0]        | LC00:              ;
 B Exit0             | ISB                ;
 Fail0:              | LDREX R1,[%x1]     ;
 MOV R2,#0           | STREX %T2,R1,[%x1] ;
 STR R2,[%ok0]       | CMP %T2,#0         ;
 Exit0:              | BNE Fail1          ;
                     | B Exit1            ;
                     | Fail1:             ;
                     | MOV R2,#0          ;
                     | STR R2,[%ok1]      ;
                     | Exit1:             ;
Observed
    0:R0=0; 1:R0=1; 1:R1=0; ok=1; x=1; y=1;