Test MP+poana+addr

Executions for behaviour: "0:R0=0 ; 1:R0=1 ; 1:R2=0 ; ok=1 ; x=1"

ARM MP+poana+addr
"PodWWANa Rfe DpAddrdR FreNaA"
Cycle=Rfe DpAddrdR FreNaA PodWWANa
Prefetch=0:x=F,0:y=W,1:y=F,1:x=T
Com=Rf Fr
Orig=PodWWANa Rfe DpAddrdR FreNaA
{ ok=1;
%x0=x; %y0=y; %ok0=ok;
%y1=y; %x1=x;
}
 P0                  | P1              ;
 MOV %T3,#1          | LDR R0,[%y1]    ;
 LDREX R0,[%x0]      | EOR R1,R0,R0    ;
 STREX %T2,%T3,[%x0] | LDR R2,[R1,%x1] ;
 CMP %T2,#0          |                 ;
 BNE Fail0           |                 ;
 MOV R1,#1           |                 ;
 STR R1,[%y0]        |                 ;
 B Exit0             |                 ;
 Fail0:              |                 ;
 MOV R2,#0           |                 ;
 STR R2,[%ok0]       |                 ;
 Exit0:              |                 ;
Observed
    0:R0=0; 1:R0=1; 1:R2=0; ok=1; x=1;