Executions for behaviour:
"1:R0=1 ; 1:R1=0 ; 3:R0=1 ; 3:R1=0 ; ok=1 ; x=1 ; y=1"
ARM IRIW+dmbana+poaa
"RfeNaA DMBdRRANa Fre RfeNaA PodRRAA FreANa"
Cycle=RfeNaA PodRRAA FreANa RfeNaA DMBdRRANa Fre
Prefetch=1:x=F,1:y=T,3:y=F,3:x=T
Com=Rf Fr Rf Fr
Orig=RfeNaA DMBdRRANa Fre RfeNaA PodRRAA FreANa
{ ok=1;
%x0=x;
%x1=x; %y1=y; %ok1=ok;
%y2=y;
%y3=y; %x3=x; %ok3=ok;
}
P0 | P1 | P2 | P3 ;
MOV R0,#1 | LDREX R0,[%x1] | MOV R0,#1 | LDREX R0,[%y3] ;
STR R0,[%x0] | STREX %T2,R0,[%x1] | STR R0,[%y2] | STREX %T2,R0,[%y3] ;
| CMP %T2,#0 | | CMP %T2,#0 ;
| BNE Fail1 | | BNE Fail3 ;
| DMB | | LDREX R1,[%x3] ;
| LDR R1,[%y1] | | STREX %T2,R1,[%x3] ;
| B Exit1 | | CMP %T2,#0 ;
| Fail1: | | BNE Fail3 ;
| MOV R2,#0 | | B Exit3 ;
| STR R2,[%ok1] | | Fail3: ;
| Exit1: | | MOV R2,#0 ;
| | | STR R2,[%ok3] ;
| | | Exit3: ;
Observed
1:R0=1; 1:R1=0; 3:R0=1; 3:R1=0; ok=1; x=1; y=1;