Test WRW+WR+poaa+dmbnaa

Executions for behaviour: "1:R0=1 ; 1:R1=0 ; 2:R1=0 ; ok=1 ; x=1 ; y=2"

ARM WRW+WR+poaa+dmbnaa
"RfeNaA PodRWAA WseANa DMBdWRNaA FreANa"
Cycle=RfeNaA PodRWAA WseANa DMBdWRNaA FreANa
Prefetch=1:x=F,1:y=W,2:y=F,2:x=T
Com=Rf Ws Fr
Orig=RfeNaA PodRWAA WseANa DMBdWRNaA FreANa
{ ok=1;
%x0=x;
%x1=x; %y1=y; %ok1=ok;
%y2=y; %x2=x; %ok2=ok;
}
 P0           | P1                  | P2                 ;
 MOV R0,#1    | LDREX R0,[%x1]      | MOV R0,#2          ;
 STR R0,[%x0] | STREX %T2,R0,[%x1]  | STR R0,[%y2]       ;
              | CMP %T2,#0          | DMB                ;
              | BNE Fail1           | LDREX R1,[%x2]     ;
              | MOV %T3,#1          | STREX %T2,R1,[%x2] ;
              | LDREX R1,[%y1]      | CMP %T2,#0         ;
              | STREX %T2,%T3,[%y1] | BNE Fail2          ;
              | CMP %T2,#0          | B Exit2            ;
              | BNE Fail1           | Fail2:             ;
              | B Exit1             | MOV R2,#0          ;
              | Fail1:              | STR R2,[%ok2]      ;
              | MOV R2,#0           | Exit2:             ;
              | STR R2,[%ok1]       |                    ;
              | Exit1:              |                    ;
Observed
    1:R0=1; 1:R1=0; 2:R1=0; ok=1; x=1; y=2;