ARM WWC+pora+dmbrna "RfeNaR PodRWRA RfeAR DMBdRWRNa Wse" Cycle=RfeNaR PodRWRA RfeAR DMBdRWRNa Wse Prefetch=1:x=F,1:y=W,2:y=F,2:x=W Com=Rf Rf Ws Orig=RfeNaR PodRWRA RfeAR DMBdRWRNa Wse { ok=1; %x0=x; %x1=x; %y1=y; %ok1=ok; %y2=y; %x2=x; } P0 | P1 | P2 ; MOV R0,#2 | LDREX R0,[%x1] | LDREX R0,[%y2] ; STR R0,[%x0] | MOV %T3,#1 | DMB ; | LDREX R1,[%y1] | MOV R1,#1 ; | STREX %T2,%T3,[%y1] | STR R1,[%x2] ; | CMP %T2,#0 | ; | BNE Fail1 | ; | B Exit1 | ; | Fail1: | ; | MOV R2,#0 | ; | STR R2,[%ok1] | ; | Exit1: | ; Observed 1:R0=1; 1:R1=0; 2:R0=1; ok=1; x=1; y=1; and 1:R0=1; 1:R1=0; 2:R0=1; ok=1; x=2; y=1;